denormals.h

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/*
 * 🍑 nectarine - denormals.h
 * Copyright (c) 2026 Fawn <rubiefawn@gmail.com>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED “AS IS” AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#pragma once
 
#include <stdint.h>
#if defined(__amd64__) || defined(_M_AMD64) || defined(__i386__) || defined(_M_IX86)
    #include <immintrin.h>
#elif defined(_M_ARM64) // MSVC arm64
    #include <intrin.h>
#elif defined(_M_ARM) // MSVC arm32
    #include <float.h>
#endif

static inline void nec_disable_denormals(void) {
#if defined(__SSE4_1__)
    // This version of the function does not check if the processor
    // supports the "denormals-are-zero" (or "DAZ") flag, and using it
    // on a processor that does not support DAZ will raise a
    // general-protection exception. Intel's manual states that DAZ is
    // "...available in most of the Pentium 4 processors and in the
    // Intel Xeon processor, with the exception of some early
    // steppings", but does not specify what those exceptions are.
    // SSE 4.1 is a conservative estimate. SSE3 might be more accurate,
    // but the only way to know for sure is to test on actual hardware.
    _mm_setcsr(_mm_getcsr() | 0x8040); // Set DAZ and FTZ both to 1
#elif defined(__amd64__) || defined(_M_AMD64) || defined(__i386__) || defined(_M_IX86)
    // https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
    // Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture
    // 11.6.3 Checking for the DAZ Flag in the MXCSR Register
    unsigned int flags = 0x8000; // FTZ
    alignas(16) uint8_t buf[512] = {0};
    #if defined(__amd64__) || defined(_M_AMD64)
        _fxsave64(buf);
    #elif defined(__i386__) || defined(_M_IX86)
        _fxsave(buf);
    #endif
    flags |= buf[28] & 0x0040; // DAZ if supported
    _mm_setcsr(_mm_getcsr() | flags);
#elif defined(_M_ARM64)
    // https://developer.arm.com/documentation/ddi0601/2026-03/AArch64-Registers/FPCR--Floating-point-Control-Register
    // https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics
    // 0x5a20 == ARM64_SYSREG(0b11, 0b011, 0b0100, 0b0100, 0b000)
    _WriteStatusReg(0x5a20, _ReadStatusReg(0x5a20) | 0x1000000);
#elif defined(_M_ARM)
    // WARN: This is untested. MSVC for ARM32 is deprecated.
    // https://learn.microsoft.com/en-us/windows/arm/arm32-to-arm64
    // https://learn.microsoft.com/en-us/windows/whats-new/deprecated-features
    // https://learn.microsoft.com/en-us/cpp/c-runtime-library/reference/control87-controlfp-control87-2
    _controlfp(0x03000000, 0x1000000); // _MCW_DN, _DN_FLUSH
#elif defined(__aarch64__)
    // https://developer.arm.com/documentation/ddi0601/2026-03/AArch64-Registers/FPCR--Floating-point-Control-Register
    uint64_t fpcr;
    __asm__ volatile ("mrs %0, fpcr" : "=r" (fpcr));
    __asm__ volatile ("msr fpcr, %0" :: "ri" (fpcr | 0x1000000));
#elif defined(__arm__)
    // https://developer.arm.com/documentation/ddi0601/2026-03/AArch32-Registers/FPSCR--Floating-Point-Status-and-Control-Register
    uint32_t fpscr;
    __asm__ volatile ("vmrs %0, fpscr" : "=r" (fpscr));
    __asm__ volatile ("vmsr fpscr, %0" :: "ri" (fpscr | 0x1000000));
#else
    #warning nec_disable_denormals() is not implemented on this architecture and will have no effect.
#endif
}

static inline void nec_enable_denormals(void) {
#if defined(__amd64__) || defined(_M_AMD64) || defined(__i386__) || defined(_M_IX86)
    _mm_setcsr(_mm_getcsr() & ~0x8040); // Set DAZ and FTZ both to 0
#elif defined(_M_ARM64)
    // https://developer.arm.com/documentation/ddi0601/2026-03/AArch64-Registers/FPCR--Floating-point-Control-Register
    // https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics
    // 0x5a20 == ARM64_SYSREG(0b11, 0b011, 0b0100, 0b0100, 0b000)
    _WriteStatusReg(0x5a20, _ReadStatusReg(0x5a20) & ~0x1000000);
#elif defined(_M_ARM)
    // WARN: This is untested. MSVC for ARM32 is deprecated.
    // https://learn.microsoft.com/en-us/windows/arm/arm32-to-arm64
    // https://learn.microsoft.com/en-us/windows/whats-new/deprecated-features
    // https://learn.microsoft.com/en-us/cpp/c-runtime-library/reference/control87-controlfp-control87-2
    _controlfp(0x03000000, 0x0000000); // _MCW_DN, _DN_SAVE
#elif defined(__aarch64__)
    // https://developer.arm.com/documentation/ddi0601/2026-03/AArch64-Registers/FPCR--Floating-point-Control-Register
    uint64_t fpcr;
    __asm__ volatile ("mrs %0, fpcr" : "=r" (fpcr));
    __asm__ volatile ("msr fpcr, %0" :: "ri" (fpcr & ~0x1000000));
#elif defined(__arm__)
    // https://developer.arm.com/documentation/ddi0601/2026-03/AArch32-Registers/FPSCR--Floating-Point-Status-and-Control-Register
    uint32_t fpscr;
    __asm__ volatile ("vmrs %0, fpscr" : "=r" (fpscr));
    __asm__ volatile ("vmsr fpscr, %0" :: "ri" (fpscr & ~0x1000000));
#else
    #warning nec_enable_denormals() is not implemented on this architecture and will have no effect.
#endif
}